1. Field of the Invention
The present invention relates to a differential amplifying circuit of the type using field effect transistors (FETs) and applicable to semiconductor integrated circuits or similar circuitry. More particularly, the present invention is concerned with a differential amplifying FET circuit with a common source connection circuit formed on a compound semiconductor (for example, gallium arsenide) substrate.
2. Description of the Prior Art
A differential amplifying circuit described above has been proposed in various forms in the past. To better understand the present invention, a brief reference will be made to some prior art differential amplifying circuits.
FIG. 1 shows a prior art differential amplifying circuit with input terminals 10 and 12. An input voltage VI and a reference voltage VR1 are applied to the input terminals 10 and 12, respectively. A differential input section 14 is connected to the input terminals 10 and 12 and has a pair of enhancement type FETs 16 and 18. The FET 16 is turned on and off by the input voltage VI, while the FET 18 is turned on and off by the reference voltage VR1. The FETs 16 and 18 have drains connected to a load section 20, and sources connected to a negative power source voltage VSS via an enhancement type FET 22. This FET 22 plays the role of a constant current source.
The load section 20 has a depletion type FET 24 connected between a positive power source voltage VDD and the drain of the FET 16, and a depletion type FET 26 connected between the power source voltage VDD and the drain of the FET 18. The FETs 24 and 26 serve as load elements. Output terminals 28 and 30 on which output voltages out1 and out2 appear, respectively, are connected to the drains of the FETs 16 and 18, respectively. In FIG. 1, the reference numeral 32 designates an input terminal assigned to a reference voltage VR2.
In operation, when the input voltage VI applied to the input terminal 10 is higher than the reference voltage VR1, the FET 16 is turned on with the result that the potential at the output terminal 28 turns from a high level or "H" to a low level or "L". Then, a current flows into the amplifying circuit via the output terminal 28. This incoming current and the current from the load FET 24 join each other and flow together into the negative power source voltage VSS via the constant current source 22. At this time, the potential at the output terminal 30 turns to a high level because the FET 18 remains in an OFF state. Consequently, a current flows out to a succeeding circuit, not shown, from the power source voltage VDD via the FET 26 and output terminal 30.
On the other hand, when an input voltage VI lower than the reference voltage VR1 arrives at the input terminal 10, the FET 16 is turned off resulting in the output terminal 28 being at a high level. As a result, a current flows out from the power source voltage VDD to the succeeding circuit via the FET 24 and output terminal 28. Since the FET 18 is an ON state, the potential at the output terminal 30 turns from a high level to a low level with the result that a current flows into the amplifying circuit via the output terminal 30. This current and a current from the FET 26 join each other and flow together into the negative power source voltage VSS via the FET 18 and constant current source 22.
The prior art differential amplifying circuit having the above construction uses the FETs 24 and 26 as load elements and selects a saturation drain current of such elements which is substantially one half the current of the constant current source 22. A drawback with this configuration is that when the input voltage VI having a great amplitude arrives, the resultant output waveform appears stepwise and is thereby degraded.
FIG. 2 shows another prior art differential amplifying circuit which is disclosed in Japanese Patent Publication No. 7522/1989. In the figures, the same components are designated by like reference numerals, and redundant descriptions will be avoided for simplicity. The circuit of FIG. 2 is distinguishable over the circuit of FIG. 1 in that depletion type FETs 40 and 42 are provided in place of the load FETs 24 and 26, and that Zener diodes 44 and 46 are respectively connected in parallel with the FETs 40 and 42 in opposite directions. In FIG. 2, the reference numerals 47 and 48 designate input terminals assigned to input voltages VI1 and VI2, respectively.
In the circuitry shown in FIG. 2, when the voltage across the FET or load 40 or 42 increases beyond a predetermined value, a current flows through the associated Zener diode 44 or 46 to reduce the load resistance of the FET 16 or 18. It follows that the output waveform is protected against deterioration even when the input voltage VI has a great amplitude. However, this prior art differential amplifying circuit has a problem left unsolved, as follows.
Specifically, when the output terminal 28, for example, is at a low level, a discharge current flows into the amplifying circuit from a succeeding circuit, not shown. Since, the sum of the discharge current and the current from the load FET 40 constitutes the current of the constant current source 22, the discharge current is limited by the current from the FET 40. On the other hand, when the potential at the output terminal 28 is changed from a low level to a high level, a charge current flows out to the succeeding circuit. At this time, the current from the load FET 40 is the charge current because the FET 16 is in an OFF state. Since the saturation drain current of the FET 40 is selected to be one half the current of the constant current source 22, such a charge current is limited by the saturation drain current. In this manner, the discharge current from and the charge current to the succeeding circuit are limited, impeding the increase in the operating speed of the circuit.